Texas Instruments TMS570LS1227 16/32-Bit RISC Flash Microcontroller
Texas Instruments TMS570LS1227 16/32-Bit RISC Flash Microcontroller (MCU) is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os. The TMS570LS1227 device integrates the ARM Cortex-R4F floating-point CPU, which offers an efficient 1.66 DMIPS/MHz and has configurations that can run up to 180MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.
The TMS570LS1227 has 1.25MB of integrated flash and 192KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a non-volatile, electrically erasable, and programmable memory. It is implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes throughout the supported frequency range.
The TMS570LS1227 features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors with up to 44 I/O terminals, seven Enhanced Pulse Width Modulator (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.
With integrated safety features and a wide choice of communication and control peripherals, the Texas Instruments TMS570LS1227 is an ideal solution for high-performance real-time control applications with safety-critical requirements.
Features
- High-performance automotive-grade microcontroller for Safety-Critical applications
- Dual CPUs running in lockstep
- ECC on Flash and RAM interfaces
- Built-In Self-Test (BIST) for CPU and on-chip RAMs
- Error signaling module with error pin
- Voltage and clock monitoring
- Arm® Cortex®-R4F 32-bit RISC CPU
- 1.66 DMIPS/MHz with 8-stage pipeline
- FPU with single- and double-precision
- 12-region Memory Protection Unit (MPU)
- Open architecture with third-party support
- Operating conditions
- Up to 180MHz system clock
- Core supply voltage (VCC) - 1.14V to 1.32V
- I/O supply voltage (VCCIO) - 3.0V to 3.6V
- Integrated memory
- 1.25MB of program Flash with ECC
- 192KB of RAM with ECC
- 64KB of Flash for emulated EEPROM with ECC
- 16-bit External Memory Interface (EMIF)
- Common platform architecture
- Consistent memory map across family
- Real-Time Interrupt (RTI) timer (OS timer)
- 128-channel Vectored Interrupt Module (VIM)
- 2-channel Cyclic Redundancy Checker (CRC)
- Direct Memory Access (DMA) controller
- 16 channels and 32 control packets
- Parity protection for control packet RAM
- DMA accesses protected by dedicated MPU
- Frequency-Modulated Phase-Locked Loop (FMPLL) with built-in slip detector
- Separate non-modulating PLL
- IEEE 1149.1 JTAG, Boundary Scan, and ARM CoreSight™ components
- Advanced JTAG Security Module (AJSM)
- Calibration capabilities
- Parameter Overlay Module (POM)
- 16 General-Purpose Input/Output (GPIO) pins capable of generating interrupts
- Enhanced timing peripherals for motor control
- 7 Enhanced Pulse Width Modulator (ePWM) modules
- 6 Enhanced Capture (eCAP) modules
- 2 Enhanced Quadrature Encoder Pulse (eQEP) modules
- Two Next Generation High-End Timer (N2HET) modules
- N2HET1 - 32 programmable channels
- N2HET2 - 18 programmable channels
- 160-word instruction RAM each with parity protection
- Each N2HET includes hardware angle generator
- Dedicated High-End Timer Transfer Unit (HTU) for each N2HET
- Two 12-bit multi-buffered ADC modules
- ADC1 - 24 channels
- ADC2 - 16 channels shared with ADC1
- 64 result buffers each with parity protection
- Multiple communication interfaces
- 10/100 Mbps Ethernet MAC (EMAC)
- IEEE 802.3 compliant (3.3V I/O only)
- Supports MII, RMII, and MDIO
- FlexRay controller with 2 channels
- 8KB of message RAM with parity protection
- Dedicated FlexRay Transfer Unit (FTU)
- Three CAN controllers (DCANs)
- 64 mailboxes each with parity protection
- Compliant to CAN protocol version 2.0A and 2.0B
- Inter-Integrated Circuit (I2C)
- Three Multi-buffered Serial Peripheral Interface (MibSPI) modules
- 128 words each with parity protection
- 8 transfer groups
- Up to two standard Serial Peripheral Interface (SPI) modules
- Two UART (SCI) interfaces, one with Local Interconnect Network (LIN 2.1) interface support
- 10/100 Mbps Ethernet MAC (EMAC)
- Packages
- 144-pin Quad Flatpack (PGE) [Green]
- 337-ball Grid Array (ZWT) [Green]
Applications
- Braking Systems (ABS and ESC)
- Electric Power Steering (EPS)
- HEV and EV inverter systems
- Battery Management Systems (BMS)
- Active Driver Assistance Systems (ADAS)
- Aerospace and avionics
- Railway communications
- Off-road vehicles
Functional Block Diagram
Related Development Tools
Texas Instruments TMDSEMU560V2STM-UE XDS560v2 System Trace
Debug probes that support both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).