Powrót do: Texas Instruments

Texas Instruments AM625SIP Arm®-Based SIP Processor

Texas Instruments AM625SIP Arm®-Based System In Package (SIP) Processor is a derivative of the ALW packaged AM6254 device with the addition of an integrated LPDDR4 SDRAM. The AM625SIP Arm-Based MPU with integrated LPDDR4 is an application processor built for Linux development. The SIP integrates 512MB of LPDDR4 with the AM6254 device, which has 4x Arm Cortex®-A53 performance and embedded features, such as 3D graphics acceleration, dual-display support, along with an extensive set of peripherals that make the SIP ideal for various industrial applications while offering optimized power architecture and intelligent features. The AM625SIP offers a simplified hardware design, optimized size/system BOM, increased robustness, and power consumption savings, enabling faster software and hardware development.

The 3-port Gigabit Ethernet switch has two external ports and one internal port with Time-Sensitive Networking (TSN) support. An additional PRU module enables real-time I/O capability for the customer’s use cases. In addition, the extensive set of peripherals included in AM625SIP enables system-level connectivity, such as USB, camera interface, MMC/SD, OSPI, CAN-FD, and GPMC for a parallel host interface to an external ASIC/FPGA. The Texas Instruments AM625SIP supports secure boot for IP protection with the built-in Hardware Security Module (HSM). It employs advanced power management support for portable and power-sensitive applications.

Features

  • Processor cores
    • Up to quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
      • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
      • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with parity protection
    • Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC
    • Dedicated device/power manager
  • Multimedia
    • Display subsystem
      • Dual display support
      • 1920x1080 @ 60fps for each display
      • 1x 2048x1080 + 1x 1280x720
      • Up to 165MHz pixel clock support with an independent PLL for each display
      • OLDI (4 lanes LVDS - 2x) and DPI (24-bit RGB LVCMOS)
      • Support safety features such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit
      • One pixel per clock or higher
      • Fill rate greater than 500Mpixels/sec
      • > 500MTexels/s, > 8GFLOPs
      • Supports at least two composition layers
      • Supports up to 2048x1080 @ 60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • One Camera Serial interface (CSI-Rx) - 4-Lane with DPHY
      • MIPI® CSI-2 v1.3 compliant + MIPI D-PHY 1.2
      • Support for 1, 2, 3, or 4-data lane mode up to 1.5Gbps per lane
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
  • Memory subsystem
    • Up to 816KB of on-chip RAM
      • 64KB of on-chip RAM (OCSRAM) with SECDED ECC, which can be divided into smaller banks in increments of 32KB for as many as two separate memory banks
      • 256KB of on-chip RAM with SECDED ECC in the SMS subsystem
      • 176KB of on-chip RAM with SECDED ECC in the SMS subsystem for TI security firmware
      • 256KB of on-chip RAM with SECDED ECC in the Cortex-M4F MCU subsystem
      • 64KB of on-chip RAM with SECDED ECC in the device/power manager subsystem
    • DDR Subsystem (DDRSS)
      • Integrated 512MB LPDDR4 SDRAM
      • Supports speeds up to 1600MT/s
      • 16-bit data bus with inline ECC
  • Security
    • Secure boot supported
      • Hardware-enforced Root-of-Trust (RoT)
      • Support to switch RoT via backup key
      • Support for takeover protection, IP protection, and anti-rollback protection
    • Trusted Execution Environment (TEE) supported
      • Arm TrustZone® based TEE
      • Extensive firewall support for isolation
      • Secure watchdog/timer/IPC
      • Secure storage support
      • Replay Protected Memory Block (RPMB) support
    • Dedicated security controller with user programmable HSM core and dedicated security DMA and IPC subsystem for isolated processing
    • Cryptographic acceleration supported
      • Session-aware cryptographic engine with the ability to auto-switch key material based on the incoming data stream
        • Supports cryptographic cores
      • AES – 128-/192-/256-Bit key sizes
      • SHA2 – 224-/256-/384-/512-Bit key sizes
      • DRBG with a true random number generator
      • PKA (Public Key Accelerator) to assist in RSA/ECC processing for secure boot
    • Debugging security
      • Secure software-controlled debug access
      • Security-aware debugging
  • PRU subsystem
    • Dual-core Programmable Real-Time Unit Subsystem (PRUSS) running up to 333MHz
    • Intended for driving GPIO for cycle-accurate protocols, such as
      • General Purpose Input/Output (GPIO)
      • UARTs
      • I2C
      • External ADC
    • 16KB program memory per PRU with SECDED ECC
    • 8KB data memory per PRU with SECDED ECC
    • 32KB general-purpose memory with SECDED ECC
    • CRC32/16 HW accelerator
    • Scratch PAD memory with three banks of 30 x 32-bit registers
    • One industrial 64-bit timer with nine capture and 16 compare events, along with slow and fast compensation
    • One interrupt controller (INTC), a minimum of 64 input events supported
  • High-speed interfaces
    • Integrated Ethernet switch supporting a total of two external ports
      • RMII(10/100) or RGMII (10/100/1000)
      • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
      • Clause 45 MDIO PHY management
      • Packet classifier based on ALE engine with 512 classifiers
      • Priority-based flow control
      • Time-sensitive networking (TSN) support
      • Four CPU H/W interrupt pacing
      • IP/UDP/TCP checksum offload in hardware
    • Two USB2.0 Ports
      • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
      • Integrated USB VBUS detection
  • General connectivity
    • 9x Universal Asynchronous Receiver-Transmitters (UART)
    • 5x Serial Peripheral Interface (SPI) controllers
    • 6x Inter-Integrated Circuit (I2C) ports
    • 3x Multichannel Audio Serial Ports (McASP)
      • Transmit and receive clocks up to 50MHz
      • Up to 16/10/6 serial data pins across 3x McASP with independent TX and RX clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and similar formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO buffers for transmit and receive (256 bytes)
      • Support for audio reference output clock
    • 3x enhanced PWM modules (ePWM)
    • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
    • 3x enhanced Capture modules (eCAP)
    • General-Purpose I/O (GPIO), all LVCMOS I/O can be configured as GPIO
    • 3x Controller Area Network (CAN) modules with CAN-FD support
      • Conforms with CAN Protocol 2.0 A, B, and ISO 11898-1
      • Full CAN FD support (up to 64 data bytes)
      • Parity/ECC check for message RAM
      • Speed up to 8Mbps
  • Media and data storage
    • 3x Multi-Media Card/Secure Digital® (MMC/SD®/SDIO) interface
      • 1x 8-bit eMMC interface up to HS200 speed
      • 2x 4-bit SD/SDIO interface up to UHS-I
      • Compliant with eMMC 5.1, SD 3.0, and SDIO version 3.0
    • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
      • Flexible 8- and 16-bit asynchronous memory interface with up to four chip (22-bit address) selects (NAND, NOR, Muxed-NOR, and SRAM)
      • Uses BCH Code to support 4-, 8-, or 16-bit ECC
      • Uses Hamming code to support 1-bit ECC
      • Error Locator Module (ELM)
        • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
        • Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
    • OSPI/QSPI with DDR / SDR support
      • Support for serial NAND and serial NOR Flash devices
      • 4GB memory address support
      • XIP mode with optional on-the-fly encryption
  • Power management
    • Low power modes supported by the device/power manager
      • Partial IO support for CAN/GPIO/UART wakeup
      • DeepSleep
      • MCU Only
      • Standby
      • Dynamic frequency scaling for Cortex-A53
  • Optimal power management solution
    • Recommended TPS65219 Power Management ICs (PMIC)
      • Companion PMIC is specially designed to meet device power supply requirements
      • Flexible mapping and factory-programmed configurations to support different use cases
  • Boot options
    • UART
    • I2C EEPROM
    • OSPI/QSPI Flash
    • GPMC NOR/NAND Flash
    • Serial NAND Flash
    • SD Card
    • eMMC
    • USB (host) boots from a mass storage device
    • USB (device) boot from external host (DFU mode)
    • Ethernet
  • Technology/package
    • 16-nm technology
    • 13mm x 13mm, 0.5mm pitch, 425-pin FCCSP BGA (AMK)

Applications

  • Human Machine Interfaces (HMI)
  • Medical equipment, patient monitoring, and portable medical devices
  • Appliance user interface and connectivity
  • Electric Vehicle Service Equipment (EVSE)/Vehicle to Infrastructure (V2X)
  • Smart home gateways
  • Embedded security (control and access panels)

Functional Block Diagram

Block Diagram - Texas Instruments AM625SIP Arm®-Based SIP Processor

Related Microprocessors

Texas Instruments AM62x/AM62x-Q1 Arm®-Based Low-Cost MPUs

For Linux® application development with scalable Arm® Cortex®-A53 performance and embedded features.

Learn Moreo Texas Instruments AM62x/AM62x-Q1 Arm®-Based Low-Cost MPUs View Productspowiązany z Texas Instruments AM62x/AM62x-Q1 Arm®-Based Low-Cost MPUs

Development Tools

Texas Instruments TMDSEMU560V2STM-UE XDS560v2 System Trace

Debug probes that support both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

Learn Moreo Texas Instruments TMDSEMU560V2STM-UE XDS560v2 System Trace View Productspowiązany z Texas Instruments TMDSEMU560V2STM-UE XDS560v2 System Trace
Opublikowano: 2025-09-19 | Zaktualizowano: 2025-09-28