Texas Instruments SN65LVDS301 27-Bit Parallel-to-Serial Transmitter
Texas Instruments SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter device converts 27 parallel data inputs to 1, 2, or 3 Sub Low-Voltage Differential Signaling (SubLVDS) serial outputs. It loads a shift register with 24-pixel bits and three control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. The pixel clock (PCLK) latches each word into the device. The parity bit (odd parity) allows a receiver to detect single-bit errors. The serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate, depending on the number of serial links used. A copy of the pixel clock is outputted as a separate differential output.
FPC cabling typically interconnects the Texas Instruments SN65LVDS301 with the display. Compared to parallel signaling, the LVDS301 outputs significantly reduce the EMI of the interconnect by over 20dB. The electromagnetic emission of the device itself is very low and meets the SAE J1752/3 ’M’-spec. The SN65LVDS301 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS inputs offer failsafe features to protect them from damage during power-up and avoid current flow into the device inputs. An input voltage of up to 2.165V can be applied to all CMOS inputs, while VDD is between 0V and 1.65V.
Features
- FlatLink™ 3G serial interface technology
- Compatible with FlatLink3G receivers such as SN65LVDS302
- Input supports 24-bit RGB video mode interface
- 24-bit RGB data, three control bits, one parity bit, and two reserved bits transmitted over one, two, or three differential lines
- Three operating modes to conserve power
- Active-mode QVGA 17.4mW (typ.)
- Active-mode VGA 28.8mW (typ.)
- Shutdown mode 0.5µA (typ.)
- Standby mode 0.5µA (typ.)
- SubLVDS differential voltage levels
- Effective data throughput up to 1755Mbps
- Bus swap for increased PCB layout flexibility
- 1.8V supply voltage
- ESD rating > 2kV (HBM)
- Pixel clock range of 4MHz–65MHz
- Failsafe on all CMOS inputs
- 80 pins 5mm × 5mm nFBGA packaging
- Very low EMI meets SAE J1752/3 ’M’-spec
Applications
- Wearables (non-medical)
- Tablets
- Mobile phones
- Portable electronics
- Gaming
- Retail automation and payment
- Building automation
Functional Block Diagram
Related Product
Texas Instruments SN65LVDS302 Display Serial Interface Receiver
Device de-serializes FlatLink™ 3G compliant serial input data to 27 parallel data outputs.