Analog Devices Inc. ADRF5532 Receiver Front Ends
Analog Devices ADRF5532 Receiver Front Ends are integrated RF, front-end multichip modules created for time division duplex (TDD) applications. The ADRF5532 incorporates a low-noise amplifier (LNA) and a high-power, silicon, single-pole double-throw (SPDT) switch.
In the receive operation at 2.6GHz, the LNA delivers a low noise figure (NF) of 1.2dB and a high gain of 35.5dB with a third-order input intercept point (IIP3) of -4dBm. In the transmit operation, the switch supplies a low insertion loss of 0.7dB and handles a long-term evolution (LTE) average power of 36.5dBm. This operation allows for an entire lifetime operation (8dB peak to average ratio (PAR)) and 39dBm for a single event (<10sec) LNA protection operation.
The ADI ADRF5532 operates from 2.3GHz to 2.7GHz in a RoHS-compliant, compact, 5mm x 3mm, 24-lead LFCSP package.
Features
- Integrated RF front-end
- LNA and high-power silicon SPDT switch
- On-chip bias and matching
- Single-supply operation
- Gain of 35.5dB typical at 2.6GHz
- Gain flatness of 0.2dB at 25°C across 400MHz bandwidth
- High-power handling at TCASE = 105°C
- Full lifetime
- LTE average power (8dB PAR) of 36.5dBm
- Single event (<10sec operation)
- LTE average power (8dB PAR) of 39dBm
- Full lifetime
- Low noise figure of 1.2dB typical at 2.6GHz
- Low insertion loss of 0.7dB typical at 2.6GHz
- High Input IP3 at -4dBm
- Low-supply current
- Receive operation at 118mA typical at 5V
- Transmit operation at 15mA typical at 5V
- Positive logic control
- 5mm x 3mm, 24-lead LFCSP package
- Pin compatible with the ADRF5534, 3.1GHz to 4.2GHz receiver front end
Applications
- Wireless infrastructure
- TDD-based communication systems
- TDD massive multiple input and multiple output (MIMO) and active antenna systems
FUNCTIONAL BLOCK DIAGRAM
Opublikowano: 2024-07-30
| Zaktualizowano: 2024-08-12