ISSI Mobile DDR SDRAM

ISSI Mobile DDR SDRAM is organized as 4 banks of 16,777,216 words x 16 bits and uses a double-data-rate architecture to achieve high-speed operation. The Data Input/Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. ISSI Mobile DDR SDRAM offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

Features

JEDEC standard 1.8V power supply
VDD = 1.8V, VDDQ = 1.8V
Four internal banks for concurrent operation
MRS cycle with address key programs
CAS latency 2, 3 (clock)
Burst length (2, 4, 8)
Burst type (sequential & interleave)
Fully differential clock inputs (CK, /CK)
All inputs except data & DM are sampled at the rising edge of the system clock
Data I/O transaction on both edges of data strobe
Bidirectional data strobe per byte of data (DQS)
DM for write masking only
Edge aligned data and data strobe output

Center aligned data & data strobe input
64ms refresh period (8K cycle)
Auto and self refresh
Concurrent auto precharge
Maximum clock frequency up to 200MHZ
Maximum data rate up to 400Mbps/pin
Power saving support
PASR (Partial Array Self Refresh)
Auto TCSR (Temperature Compensated Self Refresh)
Deep power down mode
Programmable driver strength control by full strength or 1/2, 1/4, or 1/8, of full strength
LVCMOS compatible inputs/outputs
60-Ball FBGA package