Infineon Technologies CYT3DL TRAVEO™ T2G 32-Bit Automotive MCUs
Infineon Technologies CYT3DL TRAVEO™ T2G 32-Bit Automotive MCUs are dedicated to automotive systems such as instrument clusters and Head-Up Displays (HUD). The CYT3DL MCUs feature a 2D graphics engine, sound processing, an Arm® Cortex®-M7 CPU running up to 240MHz for primary processing, and an Arm Cortex-M0+ CPU for peripheral/security processing. The MCUs include a WVGA GFX and are available in two unique packages: 216-pin TEQFP and 272-ball BGA. The Infineon TRAVEO T2G CYT3DL family products contain embedded peripherals supporting controller area networks with a flexible data rate (CAN FD), local interconnect networks (LIN), clock extension peripheral interfaces (CXPI), and Ethernet. The devices are manufactured using an advanced 40nm process. The CYT3DL TRAVEO T2G 32-Bit Automotive MCUs incorporate Infineon's low-power flash memory and multiple high-performance analog/digital peripherals and create a secure computing platform.
Features
- Graphics subsystem
- Supports 2D and 2.5D (perspective warping, 3D effects) graphics rendering
- Internal color resolution
- 2048KB of embedded video RAM memory (VRAM)
- 2x video output interfaces supporting a display from:
- Parallel RGB (1600×600 maximum display size at 40MHz)
- FPD-link single (1920×720 maximum display size at 110MHz)
- 1x capture engine for video input processing for ITU 656 or parallel RGB/YUV or MIPI CSI-2 input
- Display warping on-the-fly for HUD applications
- Direct video feed through from capture to display interface with graphics overlay
- Composition engine for scene composition from display layers
- Display engine for video timing generation and display functions
- Drawing engine for acceleration of vector graphics rendering
- Command sequencer for setup and control of the rendering process
- Supports graphics rendering without frame buffers (on-the-fly)
- Single-channel FPD-Link/LVDS interface for up to HD resolution video output
- Sound subsystem
- 4x time-division multiplexing (TDM) interfaces
- 2x pulse-code modulation-pulse width modulation (PCM-PWM) interfaces
- Up to 5x sound generator (SG) interfaces
- 2x PCM audio stream mixers with 5x input streams
- 1x audio digital-to-analog converter (DAC)
- CPU subsystem
- 240MHz (maximum) 32-bit Arm Cortex-M7 CPUs, with:
- Single-cycle multiply
- Single/double-precision floating point unit (FPU)
- 16KB data cache, 16KB instruction cache
- Memory protection unit (MPU)
- 64KB instruction and 64KB data Tightly-Coupled Memories (TCM)
- 100MHz 32-bit Arm Cortex-M0+ CPU with:
- Single-cycle multiply
- Memory protection unit
- Inter-processor communication in hardware
- 4x DMA controllers
- 240MHz (maximum) 32-bit Arm Cortex-M7 CPUs, with:
- Integrated memories
- 4160KB code-flash with an additional 128KB of work-flash
- 384KB of SRAM with selectable retention granularity
- Crypto engine
- Supports enhanced secure hardware extension (eSHE) and hardware security module (HSM)
- Secure boot and authentication
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key
- Vector unit that supports asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (ECC)
- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data
- Supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo-random number generator (PRNG)
- Galois/Counter Mode (GCM)
- Functional safety for ASIL-B
- Memory protection unit (MPU)
- Shared memory protection unit (SMPU)
- Peripheral protection unit (PPU)
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detection (BOD)
- Over-voltage detection (OVD)
- Overcurrent detection (OCD)
- Clock supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, and TCM)
- Low-power 2.7V to 5.5V operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power management
- Configurable options for robust BOD
- Wakeup support
- Up to 4x pins to wake from Hibernate mode
- Up to 61x GPIO pins to wake from DeepSleep mode
- Event generator, SCB, Watchdog timer, and RTC alarms to wake from DeepSleep modes
- Clocks
- Internal main oscillator (IMO)
- Internal low-speed oscillator (ILO)
- External crystal oscillator (ECO)
- Watch crystal oscillator (WCO)
- Phase-locked loop (PLL)
- Frequency-locked loop (FLL)
- Low-power external crystal oscillator (LPECO)
- Communication interfaces
- Up to 4x CAN FD channels
- Up to 12x runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI, or UART
- Up to 2x independent LIN channels
- Up to 2x CXPI channels with data rate up to 20kbps
- 10/100Mbps Ethernet MAC interface conforming to IEEE-802.3bw
- Serial memory interface (SMI)
- 2x SPIs (single, dual, quad, or octal), xSPI interface
- On-the-fly encryption and decryption
- Execute-In-Place (XIP) from external memory
- Timers
- Up to 50x 16-bit and 32x 32-bit Timer/Counter Pulse-Width modulator (TCPWM) blocks for regular operations
- Up to 16x Event Generation (EVTGEN) timers supporting cyclic wake from DeepSleep
- Real-time clock (RTC)
- Year/Month/Date, Day-of-week, and Hour:Minute:Second fields
- 12- and 24-hour formats
- Automatic leap-year correction
- I/O
- Up to 135x programmable I/Os
- 4x I/O types
- GPIO Standard (GPIO_STD)
- GPIO Enhanced (GPIO_ENH)
- GPIO Stepper Motor Control (GPIO_SMC)
- High-Speed I/O Standard with Low Noise (HSIO_STDLN)
- Power
- Regulators
- PMIC control module
- Programmable analog
- 1x SAR A/D converter
- ADC also supports 6x internal analog inputs:
- Bandgap reference to establish absolute voltage levels
- Calibrated diode for junction temperature calculations
- 2x AMUXBUS inputs and 2x direct connections to monitor supply levels
- ADC supports addressing external multiplexers
- ADC has a sequencer supporting autonomous scanning of configured channels
- Smart I/O
- 1x smart I/O block, which can perform Boolean operations on signals going to and from I/Os
- Up to 8x I/Os (GPIO_STD) supported
- Debug interface
- JTAG controller and interface compliant with IEEE-1149.1-2001
- Arm SWD (serial wire debug) port
- Supports Arm Embedded Trace Macrocell (ETM) trace
- Compatible with industry-standard tools, GHS MULTI or IAR EWARM for code development and debugging
- Package options
- 272-BGA, 16mm × 16mm × 1.7mm (maximum), 0.8mm ball pitch
- 216-TEQFP, 24mm × 24mm × 1.6mm (maximum), 0.4mm ball pitch
Applications
- Automotive instrument clusters
- Automotive LED front lighting
- High-performance cockpit computers
- In-vehicle infotainment (IVI) and HMI
Block Diagram
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Opublikowano: 2024-09-11
| Zaktualizowano: 2025-02-28